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Memory IC , Chips / DDR

[SDRAM] [EDO/FM] DDR

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4*16 -- DM4M16AT-266A

Product No.: DM4M16AT-266A

The DM4M16AT-266A is organized as 4 x1048576 words by 16 bits.

Eudar is proud to provide you cost efficient solution for your graphic cards and computer system.

Features

*	JEDEC standard
*	VDD=2.5V`'' 0.2V power supply
*	Double data rate architecture.
*	Cas latency- 1.5/2.0/2.5
*	Burst length- 2/4/8
*	Auto refresh and self refresh
*	SSTL_2 Interface
*	Package-400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch

16*16 -- DM16M16AT-266A

Product No.: DM16M16AT-266A

The DM16M16AT-266A is organized as 4 x4196304 words by 16 bits.

Eudar is proud to provide you cost efficient solution for your graphic cards and computer system.

Features

*	JEDEC standard
*	VDD=2.5V`'' 0.2V power supply
*	Double data rate architecture.
*	Cas latency- 1.5/2.0/2.5
*	Burst length- 2/4/8
*	Auto refresh and self refresh
*	SSTL_2 Interface
*	Package-400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch

32*8 -- DM32M8AT-266A

Product No.: DM32M8AT-266A

The DM32M8AT-266A is organized as 4 x8392608 words by 8 bits.

Eudar is proud to provide you cost efficient solution for your graphic cards and computer system.

Features

*	JEDEC standard
*	VDD=2.5V`'' 0.2V power supply
*	Double data rate architecture.
*	Cas latency- 1.5/2.0/2.5
*	Burst length- 2/4/8
*	Auto refresh and self refresh
*	SSTL_2 Interface
*	Package-400-mil, 66-pin Thin Small Outline Package (TSOP II) with 0.65mm lead pitch

128Mb D-die(x4/8) DDR SDRAM

Product No.: K4H280438D

Features

* Double-data-rate architecture; two data transfers per clock cycle

* Bidirectional data strobe(DQS)

* Four banks operation

* Differential clock inputs(CK and /CK)

* DLL aligns DQ and DQS transition with CK transition

* MRS cycle with address key programs

¡H/td> - Read latency 2, 2.5 (clock)

¡H/td> - Burst length (2, 4, 8)

¡H/td> - Burst type (sequential & interleave)

* All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

* Data I/O transactions on both edges of data strobe

* Edge aligned data output, center aligned data input

* LDM,UDM/DM for write masking only

* Auto & Self refresh

* 15.6us refresh interval(4K/64ms refresh)

* Maximum burst refresh cycle : 8

* 66pin TSOP II package

Part Number(Old)	Organization	Bank/ Interface	Refresh	Speed	Package	Power	Production Status	Comments
K4H280838D ( - )	16Mx8	4B/SSTL2	4K/64ms	B3,A2,B0,A0	66 TSOP2	C, L	Mass Production	DDR200/266, 2.5V Vdd

128Mb DDR SDRAM

Product No.: K4H280438C

Feature

* Double-data-rate architecture; two data transfers per clock cycle

* Bidirectional data strobe(DQS)

* Four banks operation

* Differential clock inputs(CK and /CK)

* DLL aligns DQ and DQS transition with CK transition

* MRS cycle with address key programs

¡H/td> - Read latency 2, 2.5 (clock)

¡H/td> - Burst length (2, 4, 8)

¡H/td> - Burst type (sequential & interleave)

* All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

* Data I/O transactions on both edges of data strobe

* Edge aligned data output, center aligned data input

* LDM,UDM/DM for write masking only

* Auto & Self refresh

* 15.6us refresh interval (4K/64ms refresh)

* Maximum burst refresh cycle : 8

* 66pin TSOP II package

Part Number(Old)	Organization	Bank/ Interface	Refresh	Speed	Package	Power	Production Status	Comments
K4H280838C ( - )	16Mx8	4B/SSTL2	4K/64ms	A2,B0,A0	66 TSOP2	C, L	Mass Production	DDR200/266, 2.5V Vdd